1. Technical Field
Integrated circuit devices (xe2x80x9cchipsxe2x80x9d) dissipate electrical energy during operation. This electrical energy is transformed into heat. Several important operating parameters of chips vary with the temperature produced by this heat. Indeed, reliable operation of a chip can only be assured below a prescribed operating temperature. Operation of a chip above its prescribed operating temperature can result in damage to the chip, damage to the computer system in which it is used and/or loss of valuable data. Consequently, the heat produced by a chip must be transferred to its surroundings at rates that ensure that the prescribed operating temperature for that chip will not be exceeded.
2. Description of Related Art
Many different heat sink apparatus have been proposed and/or employed to transfer heat from a chip to its surroundings. Those heat sinks taught in U.S. Pat. Nos. 6,116,331 and 5,926,371 are generally representative of such proposals. The heat sink apparatus shown in FIGS. 1 and 2 of this patent disclosure have, in fact, been widely used. The computer chip/heat sink literature generally shows that the operating temperature of a chip that is associated with a chip/heat sink system is largely governed by: (1) the temperature of the ambient surroundings of the chip/heat sink system, (2) the amount of electrical energy dissipated by the chip, and (3) the sum of thermal resistances and thermal interfaces along the heat transfer path leading from the chip to the ambient surroundings. Thus, changes in thermal design of any chip/heat sink system must address at least one of these three factors in ways such that the operating temperature of a given chip does not exceed some specified maximum value.
In the case of chip/heat sink systems relying only on passive direct exposure to their ambient surroundings for cooling (i.e., natural convection), most of the heat energy produced by the chip will flow through a chip/heat sink system (by conduction) and then through the interface between the surface of the heat sink system and its ambient surroundings. Such direct exposure systems have relatively low heat transfer capabilities. These low heat transfer capabilities limit the operational capabilities of many high performance chips. Hence, more complex heat transfer mechanisms (coolers) have been developed for these high performance chips. For example, active, forced air cooling (e.g., through use of fans) of a heat sink associated with a chip, permits that chip to dissipate more heat relative to a chip that relies only on direct exposure of its heat sink to the ambient surroundings. Consequently, chips having fan cooled heat sinks have been widely used with high performance chips.
The chip/heat sink manufacturing arts also have recognized that the mating surfaces of chips and heat sinks are not perfectly flat or smooth (they have microscopic peaks and valleys) and that this circumstance can diminish the system""s thermal efficiency. For example, when the mating surfaces of an chip device and a heat sink are brought into direct contact, air gaps remain over a large fraction of the total mating surface area. These air gaps contribute little to the conduction of heat from the chip to the heat sink. The prior art also has recognized that heat conduction from a chip to its heat sink can be improved by filling these air gaps with a thermal interface material which conducts heat more readily than air. Common thermal interface materials include thermal greases and elastomeric pads containing thermally conductive ceramic particles (e.g., particles of boron nitride, aluminum oxide, or magnesium oxide).
These thermal interface materials are normally used in the context of an applied pressure. The applied pressure reduces the overall thickness of the thermal interface material while causing said thermal interface material to fill more of the air gaps. In general, the higher the pressure applied between the chip device and the heat sink, the better the heat transfer between them. This pressure is usually transmitted through means of bolts that run from the heat sink to a backer plate located below the printed circuit board associated with the chip. The prior art also has recognized that the pressure exerted between a heat sink and a chip (across a thermal interface) by such bolts is not always uniform. As a result, heat transfer across such a differently pressured chip/heat sink interface is diminished to varying degrees. This remains true whether or not a thermal interface material is employed.
Thus, larger heat sinks are employed to make up for this source of diminished heat transfer. Indeed, any shortfalls or impediments in heat transfer between the chip and the ambient surroundings in which the chip/heat sink system resides, imply that larger and more expensive heat sinks need to be employed to compensate for the decreased heat transfer. Again, the consequences of not doing this (an overheated chip) are such that many heat sinks are made larger then they would be if they were more thermally efficient. Unfortunately, physical space is also at a premium in most computer systems. Hence, it is always beneficial to have chip/heat sink apparatus that are more thermally efficient, more reliable, smaller and less expensive. The heat sink devices of this patent disclosure produce all of these beneficial effects.
The heat sink device of this patent disclosure comprises a base, a core and a fan array in the form of a single, unitary piece wherein: (1) the core has a cavity system that is partially defined by a cavity wall; (2) a first array of forward fins extends from an exterior region of the heat sink device to the cavity wall; and (3) a second array of backward fins extends from an exterior region of the device to a portion of the core that lies between the cavity wall and the exterior of the device. Thus, because applicant""s heat sink device is unitary in nature, it has no internal thermal interfaces that are inherently present in any heat sink device that is comprised of separate parts that are mechanically assembled to produce an overall heat sink apparatus. Such a multi-component heat sink apparatus is shown in FIG. 2 of the present patent disclosure. It will be used to distinguish applicant""s heat sink devices from many of those taught in the prior art.
The heat sink devices of this patent disclosure will be used in conjunction with other mechanical devices. For example, they will be used in conjunction with bolts that are used to pressure the chip between the heat sink and a circuit board with which the chip is associated. To this end applicant""s heat sink is provided with an array of holes and an array of sleeves or standoffs that are respectively associated with these holes. These sleeves can be separate and distinct pieces that are mechanically associated with a given hole in the heat sink. In some of the more preferred embodiments of this invention, however, applicant""s heat sink device will further comprise an array of sleeves or standoffs that also are part of the single, unitary piece that constitutes the heat sink device. Inclusion of these sleeves in applicant""s unitary heat sink device removes those, sleeve-related, thermal interfaces found in prior art heat sinks such as that shown in FIG. 2 of this patent disclosure.
Be its sleeve construction as it may, applicant""s heat sink device is positioned between a chip and the heat sink system""s ambient surroundings. Thermal interface layers such as those previously described with respect to the prior art also may be used to thermally couple applicant""s heat sink device to the chip device it services. Thermal interface layers that require a relatively small amount of pressure between the heat sink and the upper surface of the chip in order to achieve an acceptably low value of thermal resistance between the chip device and the heat sink are generally preferred. Further referring to applicant""s chip/heat sink interface, it also should be noted that applicant""s heat sink device may have a bottom surface that is flat, or has a protruding plate-like region or has a hollowed out area (i.e., a cavity) sized to enclose the chip with which the heat sink device is associated. The cavity also may also be sized to enclose any decoupling capacitors associated with that chip. A substantially flat ceiling (i.e., upper wall) of such a cavity will be in close proximity to the chip during use. Spacers also may be positioned between the upper surface of the chip and the upper wall of such a cavity in ways that are known to this art.